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millimeterwave receiver, 57 ghz to 64 ghz data sheet hmc6301 rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2016 analog devices, inc. all rights reserved. technical support www.analog.com features frequency band: 57 ghz to 64 ghz radio frequency (rf) signal modulation bandwidth: up to 1.8 ghz noise figure (nf): 8 db typical receiver gain: 0 db to 69 db digital and analog rf and intermediate frequency (if) gain control programmable baseband gain and filter bandwidth integrated frequency synthesizer integrated image reject filter partially external loop filter support for external local oscillator (lo) on-chip temperature sensor support for 256 quadrature amplitude modulation (qam) integrated am and fm detectors universal analog i/q baseband interface 3-wire serial digital interface 75-ball, rohs compliant, wafer level ball grid array applications small cell backhaul 60 ghz industrial, scientific, and medical (ism) band data transfer multiple gbps data communication wigig/802.11ad radio high definition video transmission radar/high resolution imaging general description the hmc6301 is a complete millimeterwave receiver integrated circuit in a 6 mm 4 mm, rohs compliant, wafer level ball grid array (wlbga) that includes a low noise amplifier (lna), an image reject filter, an rf to if downconverter, an if filter, an i/q downconverter, and a frequency synthesizer. the receiver operates from 57 ghz to 64 ghz with up to 1.8 ghz of double- sided modulation bandwidth. an integrated synthesizer provides tuning in 250 mhz, 500 mhz, or 540 mhz steps with excellent phase noise to support up to 64 qam modulation. optionally, an external lo can be injected allowing for user selectable lo characteristics or phase coherent transmit and receive operation, as well as modulation up to 256 qam. support for a wide variety of modulation formats is provided through a universal analog baseband i/q interface. the receiver device also contains am and fm detectors to demodulate on-off keying (ook), frequency-shift keying (fsk), or minimum-shift keying (msk) modulation formats for lower cost and lower power serial data links without the need for high speed data converters. gain control is provided in the rf, if, and baseband stages and a low 8 db typical noise figure is supported at maximum gain. together with the hmc6300 transmitter, a complete 60 ghz transmit/receive chipset is provided for multiple gbps operation in the unlicensed 60 ghz ism band. functional block diagram vout_qm scanout data clk rfin vout_qp vout_im vout_ip interface serial bbvga mux mux 2 90 0 discr fm 3 amdet pfd div cp lpf mux refclk_m refclk_p extlo_n extlo_p amp if lna hmc6301 14424-001 figure 1.
hmc6301 data sheet rev. a | page 2 of 24 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? electrical specifications ............................................................... 3 ? recommended operating conditions ...................................... 4 ? power consumption .................................................................... 5 ? absolute maximum ratings ............................................................ 6 ? esd caution...................................................................................6 ? pin configuration and function descriptions ..............................7 ? typical performance characteristics ..............................................9 ? theory of operation ...................................................................... 12 ? register array assignment and serial interface .................... 12 ? receiver register array assignments...................................... 13 ? applications information .............................................................. 21 ? outline dimensions ....................................................................... 24 ? ordering guide .......................................................................... 24 ? revision history 9/2016v00.0716 to rev. a updated format .................................................................. universal changes to features section............................................................ 1 changes to table 1 ............................................................................ 3 changes to parameter and symbols columns, table 3 ............... 5 changes to figure 17 ...................................................................... 17 added ordering guide .................................................................. 24 7/2016revision v00.0716: initial version
data sheet hmc6301 rev. a | page 3 of 24 specifications t a = 25c, reference frequency = 71.4286 mhz, gain settings = maxi mum, if bandwidth = maximum, input impedance = 50 single ended, output impedance = 100 differential, unless otherwise noted. electrical specifications table 1. parameter test conditions/comments min typ max unit frequency range 57 64 ghz frequency step size with 71.4286 mhz reference clock 250 mhz with 142.857 mhz reference clock 500 mhz with 154.2857 mhz reference clock 540 mhz modulation bandwidth maximum bandwidth setting 3 db bandwidth 1.4 ghz 5 db bandwidth 1.8 ghz gain maximum receiver gain 63 69 db minimum receiver gain 0 db baseband gain control high and low gain settings 41 db if gain control (analog/digital) 12/15 db lna gain control (analog/digital) 20/20 db noise figure at maximum gain 8 13.5 db input minimum lna gain for 1 db compression (p1db) ?19 dbm third-order intercept (ip3) ?9 dbm temperature sensor range four levels ?40 +85 c suppression and rejection image rejection (3 lo ? if) >35 dbc sideband suppression (i/q balance) 20 23 dbc phase phase noise @ 100 khz offset ?75 dbc/hz @1 mhz offset ?93 dbc/hz @ 10 mhz offset ?114 dbc/hz @ 100 mhz offset ?122 dbc/hz phase-locked loop (pll) bandwidth using internal filter 300 khz power dissipation single-ended 0.82 w external lo 0.57 w
hmc6301 data sheet rev. a | page 4 of 24 recommended operat ing conditions table 2. parameter symbol min typ max unit power supply buffer vcc buf 2.565 2.7 2.835 v dc low noise amplifier (lna) vdd lna 2.565 2.7 2.835 v dc tripler vcc trip 2.565 2.7 2.835 v dc divider vcc div 2.565 2.7 2.835 v dc voltage controlled oscillator (vco) vcc vco 2.565 2.7 2.835 v dc intermediate frequency vcc if 2.565 2.7 2.835 v dc mixer vcc mix 2.565 2.7 2.835 v dc synthesizer vcc syn 1.3 1.35 1.48 v dc digital circuit vdd d 1.3 1.35 1.48 v dc input voltage range serial digital interface data, enable, clk, reset logic high 0.9 1.2 1.4 v logic low ?0.05 +0.1 +0.3 v reference clock reference clock, positive ref clkp lvpecl/lvds 3.3/2.5 v cmos 1.2 v reference clock, negative ref clkn v lvpecl/lvds 3.3/2.5 cmos 1.2 v baseband i/q in-phase baseband input negative (minus) vout_im 10 50 200 mv p-p positive vout_ip 10 50 200 mv p-p quadrature baseband input negative (minus) vout_qm 10 50 200 mv p-p positive vout_qp 10 50 200 mv p-p baseband i/q, common mode in-phase baseband input negative (minus) vout_im 1.3 v positive vout_ip 1.3 v quadrature baseband input negative (minus) vout_qm 1.3 v positive vout_qp 1.3 v analog gain control low noise amplifier anactrl lna 0.1 2.0 v if variable gain amplifier actl ifvga 0.1 2.25 v external lo positive extlo_p 0 3 6 dbm negative extlo_n 0 3 6 dbm drain current 1.35 v <1 ma 2.7 v 300 ma
data sheet hmc6301 rev. a | page 5 of 24 power consumption table 3. parameter voltage (v) typical current (ma) typical power consumption (mw) vcc buf 2.7 70 189 vcc lna 2.7 15 41 vcc trp 2.7 54 146 vcc div 2.7 46 124 vcc vco 2.7 52 140 vcc if 2.7 30 81 vcc mix 2.7 32 86 vcc syn 1.35 0.08 0.1 vcc d 1.35 10 13
hmc6301 data sheet rev. a | page 6 of 24 absolute maximum ratings table 4. parameter rating vcc buf 2.85 v vcc lna 2.85 v vcc trip 2.85 v vcc div 2.85 v vcc vco 2.85 v vcc if 2.85 v vcc mix 2.85 v vcc syn 1.6 v vdd d 1.6 v serial digital interface input voltage 1.5 v baseband outputs: bb, fm (each) 0.75 v p-p rf input power 0 dbm external lo power 10 dbm thermal resistance (r th ), junction to ground paddle 8.23c/w storage temperature ?55c to +150c operating temperature ?40c to 85c reflow temperature (maximum peak) 260c esd sensitivity, charged device model (cdm) class c3 (250 v) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
data sheet hmc6301 rev. a | page 7 of 24 pin configuration and fu nction descriptions ground area hmc6301 top view (ball side down) a b c d e f g h 1 2 345 6 7 8 9 10 11 12 clk scanout vout_qm vout_qp vcc buf vout_im vout_ip reset vcc div vcc div vcc div vcc div enable data gnd gnd vdd d gnd gnd extfil_p extfil_n vcc div vcc div vcc div gnd vss div vss div vss div vss div gnd vss lpf vss lpf vss lpf vss lpf rfin vss cp vss cp ref clkp gnd vdd syn vss ref vss ref ref clkn anactrl lna gnd vcc mix gnd vcc trip vreg out vss vco vss vco vcc vco vcc vco vco rcap vdd syn gnd vcc lna vcc if actl ifvga gnd vss vco extlo_n extlo_p vss vco vss vco vss vco vss vco 14424-002 figure 2. pin configuration diagram table 5. pin function descriptions pin no. mnemonic description a1 clk serial digital interface clock (1.2 v cmos). a2 scanout serial digital interface out (1.2 v cmos). a3 vout_qm quadrature negative baseband input. this pin is dc-coupled and matched to 50 . a4 vout_qp quadrature positive baseband input. this pin is dc-coupled and matched to 50 . a5 vcc buf power supply for the buffer (2.7 v dc). a6 vout_im in-phase negative baseband input. this pin is dc-coupled and matched to 50 . a7 vout_ip in-phase positive baseband input. this pin is dc-coupled and matched to 50 . a8 reset serial digital interface reset (1.2 v cmos). a9 to a12, b10 to b12 vcc div power supply for the divider (2.7 v dc). b1 enable serial digital interface enable (1.2 v cmos). b2 data serial digital interface data (1.2 v cmos). b3, b4, b6, b7, c1, d1, f1, g2, g4, h1, h5 gnd analog ground connect. b5 vdd d power supply for the digital circuits (1.3 v dc). b8 extfil_p external pll loop filter (positive). b9 extfil_n external pll loop filter (negative).
hmc6301 data sheet rev. a | page 8 of 24 pin no. mnemonic description c9 to c12 vss div digital ground for the synthesizer divider. d9 to d12 vss lpf digital ground for the synthesizer low-pass filter. e1 rfin radio frequency input. this pi n is ac-coupled and matched to 50 . e10, e11 vss cp digital ground for the synthesizer charge pump. e12 ref clkp external reference clock (positive). this pin can be dc or ac matched to 50 . f9, g12 vdd syn power supply for the synthesizer (1.3 v dc). f10, f11 vss ref digital ground for the synthesizer reference. f12 ref clkn external reference clock (negative). this pin can be dc or ac matched to 50 . g1 anactrl lna analog gain control for the low noise amplifier. leave this pin floating for digital control. g3 vcc mix power supply for the mixer (2.7 v dc). g5 vcc trip power supply for the tripler (2.7 v dc). g6 vreg out regulator output for the voltage controlled oscillator. g7, g8, h6, h9 to h12 vss vco digital ground to the synthesizer voltage controlled oscillator. g9, g10 vcc vco power supply for the voltage controlled oscillator (2.7 v dc). g11 vcc rcap external capacitor connection for the voltage controlled oscillator regulator. h2 vco lna power supply for the low noise amplifier (2.8 v dc). h3 vcc if power supply for the intermediate frequency (2.8 v dc). h4 actl ifvga analog gain control for the if variable gain amplifier. leave this pin floating for digital control. h7 extlo_n external local oscillator (negative) input. h8 extlo_p external local oscillator (positive) input.
data sheet hmc6301 rev. a | page 9 of 24 typical performance characteristics 80 40 50 45 55 65 75 60 70 57 58 59 61 60 63 62 64 gain (db) frequency (ghz) +85c +25c ?40c 14424-003 figure 3. maximum gain vs. frequency over temperature, if and rf attenuation = 0 dbm ? 5 25 00.4 0.2 0.6 0.8 1.0 1.2 2.01.8 1.4 1.6 attenuation (db) lna control voltage (v) +85c +25c ?40c 0 5 10 15 20 14424-004 figure 4. lna attenuation vs. analog control voltage over temperature, measurement taken at 60 ghz, if attenuation = 0 dbm 0 25 0123 attenuation (db) digital setting +85c +25c ?40c 5 10 15 20 14424-005 figure 5. lna attenuation vs. di gital setting over temperature, measurement taken at 60 ghz, if attenuation = 0 dbm 0 ?40 52 54 56 58 60 62 66 64 68 return loss (db) frequency (ghz) ?35 ?30 ?25 ?20 ?15 ?10 ?5 14424-006 figure 6. return loss vs. frequency ? 2 16 2.4 0 attenuation (db) analog control voltage (v) +85c +25c ?40c 0 2 4 6 8 10 12 14 0.2 0.40.6 0.8 1.0 1.2 1.41.6 1.8 2.0 2.2 14424-007 figure 7. if attenuation vs. analog control voltage over temperature, measurement taken at 60 ghz, rf attenuation = 0 dbm 0 20 0123456789101112131415 attenuation (db) digital setting 2 4 6 8 10 12 14 16 18 +85c +25c ?40c 14424-008 figure 8. if attenuation vs. di gital setting over temperature, measurement taken at 60 ghz, rf attenuation = 0 dbm
hmc6301 data sheet rev. a | page 10 of 24 0 40 0 6 12 18 30 24 36 attenuation (db) attenuation setting 5 10 15 20 25 30 35 +85c +25c ?40c 14424-009 figure 9. baseband attenuatio n vs. attenuation setting over temperature, measurement taken at 60 ghz 0 ?40 iip3 (dbm) ?5 ?10 ?15 ?20 ?25 ?30 ?35 +85c +25c ?40c 57 58 59 61 60 63 62 64 frequency (ghz) 14424-010 figure 10. input ip3 (iip3) vs. frequency over temperature, minimum lna gain, measurement taken at maximum if gain and maximum baseband attenuation 0 ?40 iip3 (dbm) ?5 ?10 ?15 ?20 ?25 ?30 ?35 +85c +25c ?40c 57 58 59 61 60 63 62 64 frequency (ghz) 14424-011 figure 11. input ip3 (iip3) vs. frequency over temperature, minimum lna gain, measurement taken at maximum if gain and maximum baseband attenuation 40 0 sideband suppression (dbc) +85c +25c ?40c 57 58 59 61 60 63 62 64 frequency (ghz) 5 10 15 20 25 30 35 14424-012 figure 12. sideband suppression vs. frequency over temperature, measurement taken at maximum gain 16 0 noise figure (db) +85c +25c ?40c 57 58 59 61 60 63 62 64 frequency (ghz) 2 4 6 8 10 12 14 14424-013 figure 13. noise figure vs. frequency over temperature 32 1 ?40 ?14 ?1 25 51 64 38 ?27 12 77 90 sensor reading temperature (c) 2 4 8 16 14424-014 figure 14. temperature sensor reading vs. temperature
data sheet hmc6301 rev. a | page 11 of 24 ? 60 ?140 1k 10k 100k 1m 100m 10m 1g phase noise (dbc/hz) frequency (hz) ?130 ?120 ?110 ?100 ?90 ?80 ?70 +85c +25c ?40c 14424-015 figure 15. phase noise vs. frequency offset over temperature, internal lo, measurement taken at 60 ghz and nominal bias ? 60 ?140 1k 10k 100k 1m 100m 10m 1g phase noise (dbc/hz) frequency (hz) ?130 ?120 ?110 ?100 ?90 ?80 ?70 +85c +25c ?40c 14424-016 figure 16. phase noise vs. frequency offset over temperature, external lo, measurement taken at 60 ghz and nominal bias
hmc6301 data sheet rev. a | page 12 of 24 theory of operation an integrated frequency synthesizer creates a low phase noise lo between 16.3 ghz and 18.3 ghz. the step size of the synthesizer equates to 250 mhz steps at rf when used with a 71.42857 mhz reference crystal or to 500 mhz if used with a 142.857 reference crystal. to support ieee channels (ism band) with a 540 mhz step size, use a 154.2857 mhz reference crystal. a 57 ghz to 64 ghz signal enters the chip through a single- ended lna input. the lna provides 20 db of variable gain. the lo is multiplied by three and mixed with the lna output to downconvert to an 8.14 ghz to 9.1 ghz sliding if. an integrated notch filter removes the image frequency at 40 ghz to 46 ghz. the if signal is filtered and amplified with 14 db of variable gain. if the chip is configured for i/q baseband output, the if signal feds into a quadrature demodulator using the lo/2 to downconvert to baseband. there are also options to use on- chip demodulators capable of demodulating am/fm/fsk/msk waveforms. the phase noise and quadrature balance of the on-chip synthesizer is sufficient to support up to 64 qam modulation. for higher order modulation up to 256 qam or less than a 250 mhz step size, the hmc6301 can operate using an external lo. the hmc6301 receiver is ideal for fdd operation along with the hmc6300 transmitter chip. however, both devices can support tdd operation by enabling and disabling the circuits. all of the enables are placed in register array 4, allowing full chip enable or disable in one spi write. there are no special power sequencing requirements for the hmc6301 ; apply all voltages simultaneously. register array assignment and serial interface the register arrays for both the receiver and transmitter are organized into 32 rows of 8 bits. using the serial interface, the arrays are written to or read from one row at a time, as shown in figure 17 and figure 18, respectively. figure 17 shows the sequence of signals on the enable, clk, and data lines to write one 8-bit row of the register array. the enable line goes low, the first of 18 data bits (bit 0) is placed on the data line, and 2 ns or more after the data line stabilizes, the clk line goes high to clock in data bit 0. the data line must remain stable for at least 2 ns after the rising edge of clk. a write operation requires 18 data bits and 18 clock pulses, as shown in figure 17. the 18 data bits contain the 8-bit register array row data (the least significant bit (lsb) is clocked in first), followed by the register array row address (row0 through row23, 000000 to 001111, lsb first), the read/write bit (set to 1 to write), and finally, the receiver chip address, 111, lsb first). the receiver ic serial interface was tested to 500 mhz, and the interface is 1.2 v cmos levels. note that the register array row address is 6 bits but only four are used to designate 32 rows, the two most significant bits (msbs) are 0. after the 18th clock pulse of the write operation, the enable line returns high to load the register array on the ic; prior to the rising edge of the enable line, no data is written to the array. the clk line should have stabilized in the low state at least 2 ns prior to the rising edge of the enable line. time = 0 enable clk 1 18 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 data lsb msb lsb msb lsb msb data array address chip address r/w = 1 14424-017 figure 17. timing diagram for writing a row of the receiver serial interface
data sheet hmc6301 rev. a | page 13 of 24 time = 0 enable clk 1 01234567 01234567 8 9 10 11 12 13 14 15 16 17 data s can out lsb msb lsb msb lsb msb lsb msb write data = (xxxxxxxx) array address chip address r/w = 0 27 read data 14424-018 figure 18. timing diagram for reading a row of the receiver serial interface receiver register array assignments all register arrays are read/write, unless otherwise noted. table 6. receiver register array assignments register array row, bit internal signal name signal function row0 row0, bit 7 lna_pwrdwn active high to power down the lna. row0, bit 6 bbamp_pwrdn_i active high to power down the baseband i channel. row0, bit 5 bbamp_pwrdn_q active high to power down the baseband q channel. row0, bit 4 divider_pwrdn active high to power down the lo divider. row0, bit 3 mixer_pwrdn active high to power down the rf mixer. row0, bit 2 ifmixer_pwrdn/ifmixer_pwrd n_i active high to power down the i channel if mixer. row0, bit 1 tripler_pwrdn active high to power down the lo tripler. row0, bit 0 ifvga_pwrdn active high to power down the if vga. row1 row1, bit 7 ipc_pwrdwn active high to power down on-chip current reference generator. row1, bit 6 ifmix_pwrdn_q active high to power down the q channel if mixer. row1, bit 5 if_bgmux_pwrdn active high to power down one of the three on-chip band gap references (if) and associated mux. row1, bit 4 ask_pwrdn active high to power down the ask demodulator. row1, bit 3 bbamp_atten1_0 controls first baseband attenuator; row1, bits[2:3]. 11 is 18 db attenuation. 10 is 12 db attenuation. 01 is 6 db attenuation. 00 is 0 db attenuation. row1, bit 2 bbamp_atten1_1 row1, bit 1 bbamp_sell_ask active high to multiplex the am detector output into the i channel baseband amplifier input. row1, bit 0 bbamp_sigshort active high to short the input to the i and q channel baseband amplifiers.
hmc6301 data sheet rev. a | page 14 of 24 register array row, bit internal signal name signal function row2 row2, bit 7 bbamp_attenfi_0 controls i channel baseband fine attenuator; row2[5:7]. 101 is 5 db attenuation. 100 is 4 db attenuation. 011 is 3 db attenuation. 010 is 2 db attenuation. 001 is 1 db attenuation. 000 is 0 db attenuation. row2, bit 6 bbamp_attenfi_1 row2, bit 5 bbamp_attenfi_2 row2, bit 4 bbamp_attenfq_0 controls q channel baseband fine attenuator; row2[2:4]. 101 is 5 db attenuation. 100 is 4 db attenuation. 011 is 3 db attenuation. 010 is 2 db attenuation. 001 is 1 db attenuation. 000 is 0 db attenuation. row2, bit 3 bbamp_attenfq_1 row2, bit 2 bbamp_attenfq_2 row2, bit 1 bbamp_atten2_0 controls second bandband attenuator; row2[0:1]. 11 is 18 db attenuation. 10 is 12 db attenuation. 01 is 6 db attenuation. 00 is 0 db attenuation. row2, bit 0 bbamp_atten2_1 row3 row3, bit 7 bbamp_selbw0 selects the low-pass corner of the baseband amplifiers; row3[6:7]. 00 is 1.4 ghz. 01 is 500 mhz. 10 is 300 mhz. 11 is 200 mhz. row3, bit 6 bbamp_selbw1 row3, bit 5 bbamp_selfastrec selects the high-pass corner of the baseband amplifiers; row3[4:5]. 00 is 45 khz. 01 is 350 khz. 10 is 1.6 mhz. row3, bit 4 bbamp_selfastrec2 row3, bit 3 bg_monitor_sel<1> for diagnostic purposes; row3[3:0] = 0011 for normal operation. row3, bit 2 bg_monitor_sel<0> row3, bit 1 if_refsel row3, bit 0 lna_refsel row4 row4, bit 7 ifvga_bias<2> controls bias and if filter alignment in the if variable gain amplifier; row4[7:1] = 1001111 for normal operation row4, bit 6 ifvga_bias<1> row4, bit 5 ifvga_bias<0> row4, bit 4 ifvga_tune<3> row4, bit 3 ifvga_tune<2> row4, bit 2 ifvga_tune<1> row4, bit 1 ifvga_tune<0> row4, bit 0 endigvga active high to enable the digital control of the if vga gain row5 row5, bit 7 ifvga_vga_adj<3> controls if variable gain amplifier; row5[7:4]. 0000 is the highest gain. 1111 is the lowest gain. row5, bit 6 ifvga_vga_adj<2> row5, bit 5 ifvga_vga_adj<1> row5, bit 4 ifvga_vga_adj<0> row5, bit 3 rfmix_tune<3> controls if filter alignment in the rf mixer; row5[3:0] = 1111 for normal operation. row5, bit 2 rfmix_tune<2> row5, bit 1 rfmix_tune<1> row5, bit 0 rfmix_tune<0>
data sheet hmc6301 rev. a | page 15 of 24 register array row, bit internal signal name signal function row6 row6, bit 7 tripler_bias<13> controls the bias of th e frequency tripler; row6[7:0] = 10111111 for normal operation. row6, bit 6 tripler_bias<12> row6, bit 5 tripler_bias<11> row6, bit 4 tripler_bias<10> row6, bit 3 tripler_bias<9> row6, bit 2 tripler_bias<8> row6, bit 1 tripler_bias<7> row6, bit 0 tripler_bias<6> row7 row7, bit 7 tripler_bias<5> controls the bias of th e frequency tripler; row7[7:2] = 011011 for normal operation. row7, bit 6 tripler_bias<4> row7, bit 5 tripler_bias<3> row7, bit 4 tripler_bias<2> row7, bit 3 tripler_bias<1> row7, bit 2 tripler_bias<0> row7, bit 1 bbamp_selfm active high to multiplex the fm detector output into the q channel baseband amplifier input. row7, bit 0 fm_pwrdn active high to power down fm demodulator. row8 row8, bit 7 lna_bias<2> controls bias of the low noise amplifier; row8[7:5] = 100 for normal operation. row8, bit 6 lna_bias<1> row8, bit 5 lna_bias<0> row8, bit 4 lna_gain<1> controls lna variable gain; row8[4:3]. 00 is the highest gain. 11 is the lowest gain. row8, bit 3 na_gain<0> row8, bit 2 ifvga_q_cntrl<2> controls the q of the if filter in the if va riable gain amplifier; row8[2:0] = 000 for the highest q and the highest gain. to redu ce q and widen bandwidth, increment row8[2:0] in the sequence: 001 100 101 111. row8, bit 1 ifvga_q_cntrl<1> row8, bit 0 ifvga_q_cntrl<0> row9 row9, bit 7 enanav_lna active high enable analog gain control of the lna. row9, bit 6 enbar_temps active high to power down the temperature sensor. row9, bit 5 en_tempflash active high to enable the temperature sensor. row9, bit 4 en_sep_ifmix_pwrdn_q enable separate powe r down for the if mixer i/q 0 for normal operation. row9, bit 3 not used not used. row9, bit 2 not used not used. row9, bit 1 not used not used. row9, bit 0 not used not used. row10 not used not used. row11 not used not used. row12 not used not used. row13 not used not used. row14 not used not used. row15 not used not used.
hmc6301 data sheet rev. a | page 16 of 24 register array row, bit internal signal name signal function row16 row16, bit 7 byp_synth_ldo factory diagnostics, 0 for normal operation. row16, bit 6 en_cpshort factory diagnostics, 0 for normal operation. row16, bit 5 en_cpcmfb enables cmfb circuit for char ge pump, set to 1 when synthesizer is in use. row16, bit 4 en_cp_dump enables auxiliary circuit for charge pump, set to 1 when synthesizer is in use. row16, bit 3 en_cptrist factory diagnostics, 0 for normal operation. row16, bit 2 en_cp enables charge pump, set to 1 when synthesizer is in use. row16, bit 1 en_synth_ldo enables ldo for synthesizer, set to 1 when synthesizer is in use. row16, bit 0 enbar_synthbg factory diagnostics, 0 for normal operation. row17 row17, bit 7 en_lockd_clk enables lock detector for synthesizer, set to 1 when synthesizer is in use. row17, bit 6 en_test_divout factory di agnostics, 0 for normal operation. row17, bit 5 en_vtune_flash enables fl ash adcs for vco vtune port, set to 1 when synthesizer is in use. row17, bit 4 en_rebuf_dc enables dc coupling for reference clock buffer. row17, bit 3 en_refbuf enables reference clock buffer, set to 1 when synthesizer is in use. row17, bit 2 en_stick_div factory di agnostics, 0 for normal operation. row17, bit 1 en_fbdiv_cml2cmos enables auxiliary circuit for the feedback divider chain, set to 1 when synthesizer is in use. row17, bit 0 en_fbdiv enables feedback divider chain, set to 1 when synthesizer is in use. row18 row18, bit 7 not used. not used. row18, bit 6 en_nb250m active high to enable 250 mhz channel step size. row18, bit 5 byp_vco_ldo factory diagnostics, 0 for normal operation. row18, bit 4 en_extlo enables external lo, set to 0 when synthesizer is in use. row18, bit 3 en_vcopk factory diagnostics, 0 for normal operation. row18, bit 2 en_vco enables internal vco, set to 1 when synthesizer is in use. row18, bit 1 en_vco_reg enables internal regulator for vco, set to 1 when synthesizer is in use. row18, bit 0 enbar_vcogb factory diagnostics, 0 for normal operation. row19 row19, bit 7 not used not used. row19, bit 6 not used not used. row19, bit 5 not used not used. row19, bit 4 not used not used. row19, bit 3 not used not used. row19, bit 2 not used not used. row19, bit 1 refsel_synthbg factory diagnostics, 1 for normal operation. row19, bit 0 muxref factory diagnostics, 0 for normal operation. row20 row20, bit 7 not used not used. row20, bit 6 fbdiv_code<6> feedback divider ratio for the integer-n internal synthesizer based on table 7, table 8, and table 9. row20, bit 5 fbdiv_code<5> row20, bit 4 fbdiv_code<4> row20, bit 3 fbdiv_code<3> row20, bit 2 fbdiv_code<2> row20, bit 1 fbdiv_code<1> row20, bit 0 fbdiv_code<0>
data sheet hmc6301 rev. a | page 17 of 24 register array row, bit internal signal name signal function row21 row21, bit 7 not used not used. row21, bit 6 not used not used. row21, bit 5 not used not used. row21, bit 4 refsel_vcobg factory diagnostics, 1 for normal operation. row21, bit 3 vco_biastrim<3> sets vco tank bias current row21[3:0] = 0010 for normal operation. row21, bit 2 vco_biastrim<2> row21, bit 1 vco_biastrim<1> row21, bit 0 vco_biastrim<0> row22 row22, bit 7 not used not used. row22, bit 6 not used not used. row22, bit 5 not used not used. row22, bit 4 vco_bandsel<4> set for desired frequency. table 7, table 8, and table 9. contain approximate band setting depending on reference clock frequency. row22[4:0] = valid range 00000-10011. row22, bit 3 vco_bandsel<3> row22, bit 2 vco_bandsel<2> row22, bit 1 vco_bandsel<1> row22, bit 0 vco_bandsel<0> row23 row23, bit 7 icp_biastrim<2> sets charge pump current. row23[7:5] = 011 for normal operation. row23, bit 6 icp_biastrim<1> row23, bit 5 icp_biastrim<0> row23, bit 4 vco_offset<0> sets internal vco output swing. row23[4:0] = 00010 for normal operation. row23, bit 3 vco_offset<1> row23, bit 2 vco_offset<2> row23, bit 1 vco_offset<3> row23, bit 0 vco_offset<4> row24 (read only) row24, bit 7 not used not used. row24, bit 6 not used not used. row24, bit 5 not used not used. row24, bit 4 not used not used. row24, bit 3 lockdet monitor for lock detect, 1 indicates valid lock. row24, bit 2 dn monitor vco amplitude. row24, bit 1 up monitor vco amplitude. row24, bit 0 center monitor vco amplitude. row25 (read only) row25, bit 7 vtune_flashp<7> vc o amplitude monitor (positive). row25, bit 6 vtune_flashp<6> row25, bit 5 vtune_flashp<5> row25, bit 4 vtune_flashp<4> row25, bit 3 vtune_flashp<3> row25, bit 2 vtune_flashp<2> row25, bit 1 vtune_flashp<1> row25, bit 0 vtune_flashp<0>
hmc6301 data sheet rev. a | page 18 of 24 register array row, bit internal signal name signal function row26 (read only) row26, bit 7 vtune_flashn<7> vco amplitude monitor (negative). row26, bit 6 vtune_flashn<6> row26, bit 5 vtune_flashn<5> row26, bit 4 vtune_flashn<4> row26, bit 3 vtune_flashn<3> row26, bit 2 vtune_flashn<2> row26, bit 1 vtune_flashn<1> row26, bit 0 vtune_flashn<0> row27 (read only) row27, bit 7 not used not used. row27, bit 6 not used not used. row27, bit 5 not used not used. row27, bit 4 temps<4> thermometer encoded temperature reading. row27[4:0] = the following: 00000 is the lowest temperature. 11111 is the highest temperature. row27, bit 3 temps<3> row27, bit 2 temps<2> row27, bit 1 temps<1> row27, bit 0 temps<0> row28 not used not used. row29 not used not used. row30 not used not used. row31 not used not used.
data sheet hmc6301 rev. a | page 19 of 24 synthesizer settings table 7. synthesizer settings, ieee channels using 154.2857 mhz reference frequency (ghz) ieee channel divider setting, fbdiv_code<5:0>, row20, bits[5:0] typical band setting, vco_bandsel<4:0>, row22, bits[4:0] 57.24 001010 00001 57.78 001011 00010 58.32 channel 1 001100 00010 58.86 001101 00010 59.40 001110 00011 59.94 001111 00011 60.48 channel 2 010000 00100 61.02 010001 00100 61.56 010010 00101 62.10 010011 00101 62.64 channel 3 010100 00101 63.18 010101 00110 63.72 010110 00110 64.26 010111 00110 64.8 channel 4 011000 00111 65.34 011001 00111 65.88 011010 01000 table 8. 500 mhz channels using 142.8571 mhz reference frequency (ghz) divider setting typical band setting 56.5 010001 00001 57 010010 00001 57.5 010011 00010 58 010100 00010 58.5 010101 00010 59 010110 00011 59.5 010111 00011 60 011000 00100 60.5 011001 00100 61 011010 00101 61.5 011011 00101 62 011100 00101 62.5 011101 00110 63 011110 00110 63.5 011111 00110 64 100000 00111
hmc6301 data sheet rev. a | page 20 of 24 table 9. 250 mhz channels using 71.42857 mhz reference frequency (ghz) divider setting typical band setting 56.5 0100010 00001 56.75 0100011 00001 57 0100100 00010 57.25 0100101 00010 57.5 0100110 00011 57.75 0100111 00011 58 0101000 00100 58.25 0101001 00100 58.5 0101010 00101 58.75 0101011 00101 59 0101100 00110 59.25 0101101 00110 59.5 0101110 00111 59.75 0101111 00111 60 0110000 01000 60.25 0110001 01000 60.5 0110010 01001 60.75 0110011 01001 61 0110100 01010 61.25 0110101 01010 61.5 0110110 01011 61.75 0110111 01011 62 0111000 01100 62.25 0111001 01100 62.5 0111010 01101 62.75 0111011 01101 63 0111100 01110 63.25 0111101 01110 63.5 0111110 01111 63.75 0111111 01111 64 1000000 01111
data sheet hmc6301 rev. a | page 21 of 24 applications information for more information about the hmc6301 evaluation kit, see the ek1hmc6350 user guide . the ek1hmc6350 contains all that is required to set up a simplex 60 ghz millimeterwave link using standard rf cable interfaces for baseband input and output. the kit comes with two motherboard printed circuit boards (pcbs) that provide on-board crystals, usb interface, supply regulators, and sma cables for connectorized i/q interfaces. software is supplied to allow the user to read from and write to all chip level registers using graphical user interface (gui) or to upload previously saved register settings. 600-01362-00-1 rx in extlo_p extlo_n rx module r3 c1 c2 c7 c14 r1 c13 c11 c9 c10 r2 c4 c5 c12 c3 c8 c6 j1 u1 j2 j3 c15 c16 14424-019 figure 19. hmc6301 (600-01362-00-1) evaluation pcb daughter board
hmc6301 data sheet rev. a | page 22 of 24 rfin anactl_lna extfil_p extfil_n extlo_n extlo_p data clk enable reset ref_clkp ref_clkn vddd scanout vcc_buf actl_ifvga vcc_mix vcc_if vco_rcap vcc_trip vcc_lna vreg_out vout_qm vout_qp vout_im vout_ip gnd vcc_div vdd_syn vss_div gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd vss_div vss_div vss_div vdd_syn vcc_div vcc_div vcc_div vcc_div vcc_div vss_cp vss_cp vss_lpf vss_lpf vss_lpf vss_lpf vss_ref vss_ref vss_vco vss_vco vcc_vco vcc_vco vss_vco vss_vco vss_vco vss_vco vss_vco vcc_div r1 1k? depop r2 1k? depop 92_mmpx-s50-0-1/111_nm-1 j5 extfl_p rx_in gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd u1 hmc6301 a12 h12 h11 h10 h9 h6 g10 g9 g8 g7 f11 f10 d12 d11 d10 d9 e11 e10 a7 a6 a10 a4 a3 b3 g6 h2 b4 d1 b6 b7 f1 g2 g4 h1 h5 c1 c12 c11 c10 c9 g12 f9 b12 b11 b10 a11 g5 a9 g11 h3 g3 h4 a5 a2 b5 f12 e12 a8 b1 a1 b2 h8 h7 b9 b8 g1 e1 vout_qp vout_qm vout_ip vout_im c2 1nf c3 1nf c4 1nf c5 1nf c6 1nf c7 1nf c8 1nf 100pf c9 c10 100nf c11 100nf rx_vcc_lna actl_ifvga rx_vcc_div rx_vcc_if rx_vcc_mix rx_vcc_buf data clk enable reset rx_refclkm rx_refclkp rx_scanout actl_lna c12 1nf c13 1nf rx_vddd extlo_p extlo_n rx_vdd_syn vss_gnd vss_gnd r3 0 rx_vcc_trip rx_vcc_vco j2 sma sma j3 vss_gnd extfl_n 1nf c14 c1 1f depop 1 3 5 7 9 2 4 6 8 10 12 14 16 18 20 ground bus 34 32 30 28 26 24 22 59 57 55 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 qth-030-01-f-d-a j4 60 58 56 54 52 50 48 46 44 42 40 38 36 actl_ifvga gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd actl_lna vout_qm vout_qp vout_im vout_ip nc gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd rx_vcc_buf rx_vddd rx_vcc_if rx_vcc_lna rx_vdd_syn rx_scanout data clk enable reset rx_vcc_div rx_vcc_vco rx_vcc_trip rx_vcc_mix rx_refclkp rx_refclkm 14424-020 figure 20. hmc6301 evaluation pcb schematic
data sheet hmc6301 rev. a | page 23 of 24 usb-led pwr-supply-led sel1 mux usb 5v supply ext clock vout ip vout im bb qp bb im bb ip vout qp vout qm fmp q fmm q fmm i fmp i bb qm 600-01205-00-2 mux sel0 12 1 2 rx module tx module dect out ref out tx ifvga tx rfvga rx lna ctl rx ifvga 60 ghz evaluation board 1 2 60 59 + + + + + + + + 1 2 60 59 r155 c82 r159 r88 j28 c2 c9 j20 fb1 fb2 fb4 fb6 c1 c10 c11 c12 c13 c14 c21 c85 c88 c24 c25 c26 c28 c3 c86 c4 c42 c43 c44 c45 c46 c47 c48 c49 c5 c50 c51 c52 c6 c63 c64 c65 c66 c67 c68 c69 c7 c70 c89 c8 c58 c93 c90 c56 u3 u15 u16 d1 d4 d7 d8 j8 r119 r157 r161 r13 r15 r17 r19 r21 r22 r23 r24 r56 r57 r58 r69 r62 r63 r64 r65 r66 r68 r67 r70 r71 r72 r73 r131 r82 r85 r86 r87 r89 r90 r91 r92 r93 r94 r95 r96 r97 r98 r99 r167 r178 r123 r128 r129 r14 r16 r18 r20 r32 r59 r77 r103 r61 r79 j10 j11 j12 j13 j14 j15 j16 j17 j18 j19 j21 j9 u19 j26 j27 j1 y1 r180 r166 r169 r168 r176 r183 r177 r172 r184 r181 r175 r174 r170 r171 c84 c87 y4 y3 u17 u18 u11 r153 r152 c79 r158 j30 c80 c81 c83 c91 c92 c95 c94 r130 r154 r156 r160 r162 r163 r60 r165 r173 r182 r179 r164 u22 j31 j32 j33 j34 j29 c102 c101 c110 c96 c105 c99 c108 c103 c97 c106 c100 c109 u27 u26 u23 u24 r186 r195 r188 r189 r187 r190 r191 r192 r193 u25 c104 c98 c107 r194 r185 14424-021 figure 21. hmc6301 evaluation pcb motherboard
hmc6301 data sheet rev. a | page 24 of 24 outline dimensions 0.815 0.755 0.695 6.050 6.000 5.950 bottom view (ball side up) top view (ball side down) side view 0.220 0.190 0.160 0.595 0.565 0.535 0.310 0.270 0.230 4.050 4.000 3.950 3.50 ref 5.50 ref 5.75 ref coplanarity 0.10 seating plane 01-25-2016-a 0.50 bsc 0.25 bsc 0.25 bsc p kg-005030 0.50 bsc 0.40 bsc ball a1 identifier 0.65 0.15 0.25 0.635 0.485 ground area a b c d e f g h 12345678 9 101112 figure 22. 75-ball wafer level ball grid array [wlbga] (bf-75-1) dimensions shown in millimeters ordering guide model temperature range chip bump composition msl rating 1 package description package option package marking 2 hmc6301bg46 ?40c to +85c 96.5 tin (sn), 3.0 silver (ag), 0.5 copper (cu) msl1 75-ball wlbga bf-75-1 bbfz #yyww xxx xxxxx-xx EV1HMC6301BG46 evaluation board, pcb only ek1hmc6350 evaluation kit assembly 1 maximum peak reflow temperature of 260c. the peak reflow temperature must not exceed the maximum temperature for which the pa ckage is qualified according to the moisture sens itivity level (msl1). 2 bbfz indicates a pb-free part, #yyww indicates the year and week number, and the assembly lot number is indicated by xxx xxxxx x-xx. ?2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d14424-0-9/16(a)

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